1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device. In particular, the present invention relates to a semiconductor integrated circuit device including a non-volatile memory system having a pseudo pass function.
2. Description of the Related Art
If a non-volatile semiconductor memory device, for example, NAND flash memory is used, bit error detection and correction by ECC (Error Checking and Correcting) are effective for ensuring sufficient reliability. For example, a standard system using a multi-value NAND flash memory has a built-in ECC, which enables four-symbol bit error detection and correction per page.
High integration and large capacity have advanced in the NAND flash memory. In such a NAND flash memory having high integration and large capacity, the following phenomenon has been recently reconfirmed. According to the phenomenon, the threshold value of a certain memory cell suddenly becomes high; as a result, data is not correctly written or erased. This phenomenon is called “sudden bit error” in the following description.
In view of the foregoing circumstances, the following concept has been known. For example, in the multi-value NAND flash memory, it is advantageous in terms of cost to allow the “sudden bit error” to some degree, to ensure reliability. A function developed based on the foregoing concept is a so-called “pseudo pass function”. The “pseudo pass function” is a method of returning a “pass” as the status even if a bit error occurs in one or two bits when chip internal write or erase sequence is completed. For example, the foregoing method has been disclosed in U.S. Pat. No. 6,185,134 and Japan Patent Registration No. 3178912. More specifically, even if the bit error occurs when chip internal write or erase sequence is completed, ECC is carried out in a system or flash controller in the read operation. For this reason, no hindrance arises so long as the bit error is within a range of the number of correctable bits.
However, the mechanism is such that the foregoing “pseudo pass function” is issued after write or erase pulse is applied by a predetermined number of times. For this reason, the following problem arises. In order to carry out write or erase with respect to pages or blocks having bits incapable of permanently writing or erasing, a pulse is applied by a predetermined number of times. For this reason, a write or erase speed is reduced; as a result, this is a factor leading to reduction in the performance of an electronic apparatus system using a NAND flash memory, for example, a memory card.